The present invention pertains to a method and system using photolithography to produce aligned emitter tips in field emission display devices.
Field emission display (FED) technology utilizes a matrix addressable array of pointed, thin film, cold field emission cathodes in combination with a phosphor luminescent screen, as represented by for example U.S. Pat. No. 5,210,472, the disclosure of which is incorporated herein by reference. An emission flat panel display operates on the principle of cathodoluminescent phosphors excited by cold cathode field emission electrons. A faceplate having a cathodoluminescent phosphor coating receives patterned electron bombardment from an opposing cathode member thereby providing a light image which can be seen by a viewer. The faceplate is separated from the cathode member by a vacuum gap and the two plates, in some embodiments, are prevented from collapsing together by physical standoffs or spacers fixed between them. In some embodiments, the cathode member is integrally formed with a baseplate, while in others, the cathode member is connected to the faceplate and a backplate surrounding the cathode member is sealed to the faceplate, and the vacuum exists between the faceplate and the backplate.
The cathode member of a field emission display is comprised of arrays of emission sites (emitters) which are typically sharp cones that produce electron emission in the presence of an intense electric field, an extraction grid disposed relative to the sharp emitters to provide the intense positive voltage for the electric field, and a means for addressing and activating the generation of electron beams from those sites. Varying the charge, which is delivered to the phosphor in a given pixel from an emission array, will vary the light output (brightness) of the pixel associated with it. The duration of the persistence is a material property which can be varied and controlled by the selection and syntheses of the phosphor materials used. Two techniques for varying the charge delivered by an emission array are either to vary the time period that the site is activated or alternatively to vary the emission current.
Fabrication of FEDs utilizes high resolution lithography and etching to create openings in a metal-dielectric sandwich. The extraction grids have been formed by a combination of deposition, polishing and wet etching. A silicon dioxide dielectric layer is deposited superadjacent to the emitter tips with a thickness such that the sum of the conductive layers with the previously deposited dielectric thickness is greater than tip height. The surface of the deposited conductive material is removed by a wet polishing process using an aqueous based slurry and a conforming polishing pad, known as the "CMP" or chemical-mechanical-planarizer process. For example, see U.S. Pat. No. 5,229,331, incorporated herein by reference. Such a CMP process produces self-aligned emitters due to the use of the tip itself as the reference from which subsequent steps are carried out. However, this process provides low yield due to the rough treatment inherent in the CMP process. Therefore, there is a need for a process for manufacturing emitter tips that results in a higher yield than the traditional CMP process, while still giving acceptable yields.
To illustrate this process, FIG. 1 shows a CMP process of forming an emitter tip and grid structure wherein the tip 10 is formed by placing a photoresist mask or cap 12 over the substrate 14 which is then etched, according to processes known in the art, to removed the portion shown in broken lines to form emitter tip 10. The etching occurs more slowly under the mask or cap, thus generating the tip 10. For example, see U.S. Pat. No. 5,391,259, incorporated herein by reference. Next the mask or cap 12 is removed and the tip 10 is further sharpened by known processes (not shown).
Referring now to FIG. 2, after the tip 10 has been sharpened, a layer of insulator (for example silicon dioxide) 16 is laid over the tip 10 and a grid layer 18 of, for example, alpha silicon is also laid over the tip. Next, chemical-mechanical-planarization is performed at the level of dashed line 20.
Referring now to FIG. 3, an etch that is selective for the silicon dioxide layer 16 is used to expose emitter tip 10. Thus an aligned gate-emitter structure is generated. However, as discussed above, the disadvantage in the above mentioned chemical mechanical planarization method is that it is a very rugged and destructive process. An alternative prior art method of forming a gate structure uses a nitride cap (not shown) throughout the process of forming the grid. For example see U.S. Pat. No. 5,049,520, incorporated herein by reference. The disadvantage of using a nitride cap is that the cap must be balanced on an emitter tip. Should the cap fall during formation of the gate, it cannot be easily removed and the entire structure may have to be abandoned and scrapped. According to the present invention these disadvantages are avoided.